CUDA 13.5 Opens a Bigger Era for Vera Rubin AI Computing

NVIDIA CUDA 13.5 has reached general availability, bringing production-ready support for the NVIDIA Vera Rubin GPU architecture and extending Windows on Arm support to NVIDIA DGX Station for Windows. The release also gives developers more control over GPU partitions, multi-process workloads, multi-GPU communication, Python tooling, and core libraries.

That makes CUDA 13.5 more than a routine software update. It connects new hardware with the controls and programming tools needed to run demanding AI workloads, while NVIDIA’s wider ecosystem pushes toward larger inference deployments, open platforms, and specialized intelligence.

Vera Rubin Support Arrives for Production Workloads

The headline change is clear: CUDA 13.5 now supports NVIDIA Vera Rubin in production. Developers can also use Windows on Arm with NVIDIA DGX Station for Windows, extending the platform options available for CUDA workloads.

CUDA 13.5 adds locality domain controls that let applications choose between uniform streaming multiprocessor partitions across locality domains or partitions that include all available SMs. By default, localized green-context partitions use the same guaranteed SM count per domain, leaving supplemental SMs outside those partitions.

The new cudaDevSmResourceGroupLocalityDomainSupplementalSms flag works with cudaDevSmResourceGroupLocalityDomainId to include those additional SMs within each selected domain. Applications can then use discovery mode in cudaDevSmResourceSplit() to obtain each partition’s SM count and distribute work according to the available capacity.

This gives developers a clearer way to match workloads with GPU resources. A system can preserve uniform partitions for predictable placement, or include every available SM when a workload needs the widest partition possible.

MPS v3 Brings More Control to Shared GPUs

NVIDIA Multi-Process Service, or MPS, v3 adds controls designed for servers that host multiple workloads. Weighted timeslicing lets operators give longer compute turns to servers hosting workloads that need them, while SM partition load balancing lets workloads use capacity beyond their base partition when resources are available.

Enable borrowing with –max-chunks. A partition can lend its SMs while it has no attached clients with –shareable=true. These settings work independently, so a partition can borrow, lend, or do both. MPS reclaims borrowed resources before reassigning them, while applications continue to see a stable base partition size.

The release also ties workload organization to MPS resource policies through cgroup-based routing. A cgroup v2 subtree can map to an MPS namespace, and clients connecting through the daemon’s main socket route to that namespace automatically.

Per-namespace SM partition assignments let operators choose a partition for each device once, then apply that selection to every client routed to the namespace. Clients no longer need separate CUDA_MPS_SM_PARTITION settings. Namespace assignments take precedence, while devices without an assignment retain the environment-variable fallback.

Memory accounting gains a polling-based fallback when cgroup threshold notifications are missing or unreliable. During eviction decisions, MPS can read current usage and limits instead of relying on cached notification state. To force polling, run nvidia-cuda-mps-control memacct set force_polling=true before memory accounting starts, though this adds work per eviction decision.

CUDA Tile, Python, and Libraries Expand the Toolkit

CUDA Tile gains multi-GPU communication through unicast and multicast pointers on NVLink and NVSwitch fabrics. It also includes a public preview of SIMT interoperability, allowing Tile kernels to call device functions from libraries such as NVSHMEM, CCCL Coop, Warp, and MathDx.

CUDA Python cuda.core 1.2 introduces batched memory copies through copy_batch(), Programmatic Dependent Launch through LaunchConfig, and more flexible CUDA Graph updates without reinstantiation. These changes target the repeated setup and coordination tasks that can slow complex GPU applications.

CCCL 3.5 adds public tuning APIs for CUB, reproducible floating-point scans, and batched Top-K selection integrated into FlashInfer. It also provides data-dependent reductions that consume element counts from device memory using cuda::args::deferred.

The broader CUDA platform now includes over 1000 co-designed domain-specific libraries, exceeding 1,500 across the expanding software ecosystem. CUDA 13.5 strengthens that foundation by giving developers more ways to control resources, connect GPUs, and shape execution around real workloads.

Inference Expansion Pushes the Ecosystem Forward

The release arrives alongside major activity around enterprise inference. ZStack is open-sourcing GPUWorks, a lightweight, enterprise-grade AI inference platform, under the Apache License 2.0. The platform is described as a 40MB platform to manage a thousand GPU servers.

Fireworks will expand its capacity in Europe with NVIDIA Vera Rubin and Grace Blackwell Platforms. The planned expansion will also use the NVIDIA DSX AI factory platform and NVIDIA Spectrum-X Ethernet networking for performance and throughput per watt. The NVIDIA accelerated computing footprint will support deployments across Europe beginning in 2027.

At Fireworks Forge, its inaugural user conference, Fireworks introduced an Ultrafast inference preview for interactive applications that need immediate responses, multi-day prompt caching and background mode for long-running agents, and higher rate limits to support growing demand.

“With NVIDIA, we’re expanding our European capacity with the Vera Rubin and Grace Blackwell Platforms to help more enterprises run specialized intelligence at scale,” said Lin Qiao, co-founder and CEO of Fireworks. Qiao also said, “Improving inference across the full spectrum of enterprise workloads will change the very nature of work, from interactive applications that need immediate responses to agents that keep working in the background. Every enterprise needs the speed, efficiency, and capacity to support both.”

Jensen Huang, founder and CEO of NVIDIA, said, “The intelligence of open models has reached an inflection point, opening the door for enterprises to build specialized AI that transforms how they work.” He added, “I’m delighted to see demand for Fireworks skyrocketing,” and said NVIDIA and Fireworks are expanding computing capacity with Vera Rubin and Grace Blackwell to bring specialized intelligence to more enterprises.

The hardware pipeline is expanding too. Samsung is expected to make RAM for Nvidia and AMD at a new chip factory in Taylor, Texas. AMD has reserved most of the RAM from Samsung’s second Taylor, Texas chip plant, with some also going to Nvidia, and mass production is expected to start in 2030 using Samsung’s advanced 2-nanometre technology.

CUDA 13.5 sets the software foundation for this next phase, linking Vera Rubin support with finer GPU partitioning, stronger multi-GPU communication, and tools built for enterprise inference. As deployments grow across Europe beginning in 2027, those controls will shape how efficiently specialized AI moves from powerful hardware into real workloads.

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