Edge AI Moves Toward Modular Silicon Partnerships

Edge AI is becoming a subsystem problem. On November 9, 2026, Expedera announced a pre-silicon pairing of its Origin Evolution neural processing unit (NPU) IP with Cadence’s Tensilica NeuroEdge 130 AI Co-Processor. The demonstration shows how the two semiconductor IP blocks divide and execute AI inference workloads before customer silicon exists.

Expedera describes the result as a validated pre-silicon integration, not a customer-silicon benchmark. The combined subsystem is designed to improve performance and power efficiency while reducing latency, cost and complexity—but the announcement supplies no combined measurements for those goals. Silicon marketing remains a place where adjectives often arrive before numbers.

A Division of Labor Inside the AI Subsystem

The arrangement does not assign identical work to two accelerators. Amol Borkar, group director of product management and marketing for Cadence’s Tensilica Products Group, said the NeuroEdge 130 assists Expedera’s NPU with pre-processing, post-processing and operator fallback while also executing AI networks.

Cadence designed the co-processor to work alongside Neo NPUs, customer-developed NPUs or third-party NPU IP. The Expedera pairing provides a concrete example of that third-party route, targeting inference designs across edge nodes, smartphones, automotive systems and data centers; the approach can also extend to other Tensilica digital signal processors.

Cadence’s product documentation describes an Xtensa-based architecture using very long instruction word (VLIW) and single instruction, multiple data (SIMD) techniques. Optimized instructions handle operations such as sigmoid, tanh and ReLU, which are less suited to NPUs, while the NeuroEdge 130 can issue instructions and commands to an NPU as a control processor.

That programmability covers workloads not anticipated when the subsystem was designed. The NeuroEdge 130 connects through AXI or Cadence’s High Bandwidth Direct Interface, and the NeuroWeave software development kit, built on the Tensor Virtual Machine stack, tunes, optimizes and deploys models on Cadence AI IP.

Sharad Chole, Expedera’s chief scientist, said models are running on the combined subsystem. He also said agentic AI workflows are helping Expedera deliver customized IP more quickly, describing the approach as “a faster, lower-risk path to production edge AI tailored to their performance and power requirements.”

Scaling From Neural IP to Broader Systems

Origin Evolution breaks neural networks into packets, or contiguous fragments, and routes them through Feed Forward, Attention and Vector processing blocks. Those blocks handle different operations, data types and precisions, while the NPU supports LLMs, CNNs, RNNs and custom or black-box layers.

The packet design aims to reduce large memory movements and let different kinds of network work share one architecture. Origin Evolution debuted on May 20, 2025 as available, production-ready and silicon-proven in customer production designs; Expedera reports scalability to 128 TFLOPS in one core and petaFLOPS and beyond with multiple cores.

Expedera also reports a reduction of more than 75% in external memory moves for Llama 3.2 1B and Qwen2 1.5B compared with alternativ. Those figures describe Origin Evolution’s reported behavior, not the new combined subsystem, a distinction that matters when a pre-silicon demonstration starts wearing benchmark clothing.

The broader semiconductor push follows the same modular logic. NXP announced a unified robotics platform built on its Neural Axis Architecture, described as a distributed foundation connecting sensing, real-time control, AI processing and communication. Its press release positions the platform around a modular, open-source software development kit and ready-to-use reference designs integrating AI, connectivity, motor control, security and energy management.

NXP also describes pre-validated interoperable subsystems that scale from individual functions to complete systems, with an initial drone functionality available in 30 minutes out of the box. Support is expanding to service robots and autonomous systems—because apparently even drones now need a faster onboarding experience.

GigaDevice will showcase embedded technologies and application-oriented solutions at electronica 2026, including a six-axis collaborative robotic arm powered by the GD32H77R MCU. The MCU uses an Arm Cortex-M7 core running at up to 600 MHz for high-performance, real-time joint control, with absolute encoder feedback and EtherCAT-based CoE communication using CiA 402 drive profiles for precise positioning and coordinated motion.

The company will also present three GD32H7-based GUI solutions: a Qt for MCUs display supporting rich widgets, multilingual input, multimedia and real-time data visualization; a GD32H77D solution combining hardware-accelerated 2D graphics with an MIPI-DSI interface; and a GD32H7 emWin solution with video playback, audio decoding and customizable components.

GigaDevice’s demonstrations extend into automotive systems, including body control, vehicle connectivity and digital instrumentation. The GD32A7 Body Control Module includes functional safety and information security capabilities, while the GD32A714 Automotive 4G Telematics Box supports remote control, diagnostics and over-the-air updates through CAN communication and hardware security resources; FPT Software developed a motorcycle instrument cluster showing speed, battery status and temperature alongside vehicle-system interfaces.

Behind those systems sits GigaDevice’s GD25/55 Flash memory portfolio for code storage, system boot and firmware management. HTEC’s semiconductor research adds a less comfortable measure of progress: 48% of semiconductor respondents describe their organizations as scaling AI or already AI-native, compared with 44% across the overall sample, while 78% report increased investment over the past year versus 79% overall.

Only 22% say AI’s purpose, value and expected outcomes are clearly articulated across their organizations, and 83% agree that people and processes constrain AI value more than technology does. Among 200 semiconductor executives and technology leaders surveyed across the United States, United Kingdom, Germany, Saudi Arabia and the United Arab Emirates, 45% prioritize alignment with growth or differentiation, while 36% require a formal ROI model before approval.

HTEC found that 38% report AI value case by case, compared with 30% across the wider sample, while 28% use an enterprise dashboard compared with 36% overall. Only 22% actively monitor adoption and outcomes across functions, 21% provide comprehensive AI enablement for non-technical employees, and 57.5% measure AI risk alongside value only for high-risk use cases; 16% do so across their AI portfolio, while 33% of technical respondents identify model unpredictability and edge cases as the main complication for human-in-the-loop oversight.

Craig Melrose, HTEC’s Global Managing Partner, said, “Semiconductor companies know how to measure engineering performance. The next challenge is applying the same discipline to AI value.” The Expedera-Cadence integration addresses the hardware side of that equation, but its missing combined measurements leave the business case unfinished.

AMD’s announcement adds the data-center angle: 5th Gen AMD EPYC processors power the host infrastructure for Google Cloud TPU 8tx, described as the first cloud Tensor Processing Unit system with hardware-enforced confidential computing. AMD says EPYC processors protect sensitive AI models and data while combining host processing, security capabilities and x86 software compatibility, and serve as the host CPU of choice across more than 10 leading hyperscalers and frontier AI labs spanning GPUs and custom AI accelerator ASICs.

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